The invention relates to a data bus for serial data transmission between apparatus which are capable of transmitting and/or receiving data via the data bus, recessive and dominant states being present on the data bus and a respective bit value being associated with each of said states.
For data buses of this kind it is nowadays desirable to interrupt a message currently being transmitted when a message of higher priority is to be transmitted. In most cases this is possible only subject to given conditions, because either a very intricate mechanism is provided so as to privilege urgent messages or an urgent message cannot really be transmitted immediately, or additional transmission channels are provided in order to signal an urgent message.
For example, according to U.S. Pat. No. 5,546,392 an additional transmission channel is provided so as to signal an urgent message.
It is an object of the invention to provide a serial data bus in which a message of low priority in a channel can be interrupted at any time and immediately by a message of higher priority, so that, if desired, the message of higher priority can be transmitted on the data bus without delay.
This object is achieved according to the invention in that messages are transmitted in message blocks, each message block having at its beginning a start block with (n+k) dominant bits and j subsequent recessive bits and subsequent data blocks with n data bits and m subsequent recessive bits, that a message block of low priority currently being transmitted can be interrupted by another apparatus in order to transmit a message block of higher priority in that said other apparatus generates a new start block on the data bus and subsequently transmits the associated data blocks, and that an apparatus transmitting a message block on the data bus continuously checks whether a start block appears on the data bus and interrupts the transmission of its message block, if necessary.
Two states exist on the serial data bus: the recessive state and the dominant state. Different bit values are assigned to the two states; for example, the bit value zero is assigned to the dominant state and the bit value one to the recessive state. The bus may then be configured, for example, in such a manner that a transmitting source realizes the dominant state in that it reduces the amplitude of the bus to zero or substantially zero. The recessive state can be realized by way of high impedance behavior of the source, since the bus then automatically assumes a high level. The bus also assumes the recessive state in the absence of message transmission.
For the data bus according to the invention the form in which messages are transmitted is defined. Transmission takes place in the form of message blocks, each message block having a start block at its beginning and subsequently at least one data block. Given formats are defined for the start blocks as well as for the data blocks. For example, for each start block at the beginning of a message block it is defined that it should include n+k dominant bits and j subsequent recessive bits. Data blocks, however, contain at the most n data bits which are succeeded by m subsequent recessive bits. From this definition it already follows that a start block must be concerned when more than n dominant bits appear on the bus, because data blocks contain at the most n data bits and hence, even when the n data bits are all dominant, no more than n dominant bits can appear in succession in a data block, because each data block is always succeeded by m subsequent recessive bits. Unambiguous identification of the start blocks is thus obtained already. For the data bus according to the invention there are also defined message blocks of different priority. At least two priorities are provided, said priorities being configured so that a message block of lower priority which is being transmitted can be interrupted at any time and immediately by a message block of higher priority. This is realized in that the sender of the message block of higher priority generates a start block of the message block of higher priority on the data bus. This also takes place during the transmission of the message block of lower priority. The sender of the message block of higher priority realizes the foregoing by generating n+k dominant bits on the data bus as the start block. For this purpose use may also be made, if desired, of dominant bits of the transmitted message block of lower priority. However, recessive bits of the message block of lower priority may also be overwritten by dominant bits. It is only important that the sender of the message block of higher priority generates n+k dominant bits with j subsequent recessive bits on the data bus.
The transmission of the message of higher priority can be successful only if the sender of the message of lower priority interrupts the transmission of the relevant message block upon recognition of a start block on the data bus. Therefore, for the data bus according to the invention it is also necessary that a sender of a message continuously monitors the data bus for the appearance of a start block from another sender on the data bus. In that case the sender must interrupt his message. Similarly, a receiver continuously checks whether a new start block appears. If this is the case before the reception of the previous message has been duly completed, the reception is interrupted and the reception of a new message commences after the start block.
It is thus achieved that a message block of higher priority can interrupt the transmission of a message block of lower priority at any time by generating a start block of the message of higher priority on the bus.
No additional channels or signaling are required for the coordination of the message blocks of the various priorities on the bus. A current message of lower priority can indeed be extremely simply interrupted by a message of higher priority on the data bus according to the invention. It is also ensured that the urgent message can indeed be transmitted immediately and that it is not necessary to wait a given period of time so as to complete a message already present on the bus or to execute a decision process. Because of the simplicity of the procedure, the data bus according to the invention can be extremely simply implemented. by the defined apparatus.
Moreover, as in a further embodiment of the invention it may also be advantageously predetermined which message, and hence also which message block, is allowed to interrupt other currently transmitted message blocks.
As is realized in a further embodiment of the invention, in the simplest case a currently transmitted message block may already be interrupted when the (n+1)th bit of a data block on the data bus is dominant. In that case it can already be expected that another sender generates a start block on the bus, even though the n+k necessary dominant bits are not yet present on the bus. In this manner the fastest possible interruption of the transmission of the data block of lower priority can be realized.
However, if it must be reliably ensured that a start block is indeed concerned, it may be advantageous, as in a further embodiment of the invention, that the transmitting apparatus interrupts the transmission of its message block only if a defined number of bits between the n+1th and the (n+k)th bit on the bus is dominant. Depending on the selected predetermined number, a high degree of reliability can be achieved that not a data error is concerned but a start block from another transmitting apparatus.
In the simplest case, as in a further embodiment of the invention, a transmitting apparatus can already interrupt its message block when a bit by bit check reveals that a bit transmitted as being recessive is actually dominant on the data bus. In that case either the start block of another transmitting apparatus or a data error is concerned.
When an apparatus wishes to transmit a message of higher priority on the data bus and hence interrupt a message block of lower priority being transmitted on the data bus, a start block with n+k dominant bits must be generated. To this end, during a phase in which the recessive bits are generated in the second message, the transmitting apparatus can replace these bits by n+k dominant bits. However, as in a further embodiment of the invention, the apparatus can also involve dominant bits of the message block of lower priority being transmitted in the generation of the dominant bits of its start block. It can thus also utilize dominant bits of the message block of lower priority in order to generate the dominant bits of its start block. This enables even faster interruption and hence also faster transmission of the message block of higher priority.
In order to minimize the time losses, notably for the start block, and also the time required for the recessive bits at the end of the blocks, in a further embodiment of the invention the number of recessive bits in the start blocks and the data blocks each time amounts to only one and the number of dominant bits of a start block is one bit larger than the number of data bits in the data blocks. The procedure for the data bus according to the invention can thus be executed already and only a minimum additional amount of time is required for the recognition of the start blocks.
The simplest case may involve only messages of two priorities as in a further embodiment of the invention. This makes it very simply clear which message may interrupt other messages.
The steps described in claim 11 may be advantageously used to signal the priority of a transmitted message.